module core(
  input clock,
  input reset,
  input io_interrupt,

  input io_master_awready,
  output io_master_awvalid,
  output [31:0] io_master_awaddr,
  output [3:0] io_master_awid,
  output [7:0] io_master_awlen,
  output [2:0] io_master_awsize,
  output [1:0] io_master_awburst,

  input io_master_wready,
  output io_master_wvalid,
  output [63:0] io_master_wdata,
  output [7:0] io_master_wstrb,
  output io_master_wlast,

  output io_master_bready,
  input io_master_bvalid,
  input [1:0] io_master_bresp,
  input [3:0] io_master_bid,

  input io_master_arready,
  output io_master_arvalid,
  output [31:0] io_master_araddr,
  output [3:0] io_master_arid,
  output [7:0] io_master_arlen,
  output [2:0] io_master_arsize,
  output [1:0] io_master_arburst,

  output io_master_rready,
  input io_master_rvalid,
  input [1:0] io_master_rresp,
  input [63:0] io_master_rdata,
  input io_master_rlast,
  input [3:0] io_master_rid,

  output io_slave_awready,
  input io_slave_awvalid,
  input [31:0] io_slave_awaddr,
  input [3:0] io_slave_awid,
  input [7:0] io_slave_awlen,
  input [2:0] io_slave_awsize,
  input [1:0] io_slave_awburst,

  output io_slave_wready,
  input io_slave_wvalid,
  input [63:0] io_slave_wdata,
  input [7:0] io_slave_wstrb,
  input io_slave_wlast,

  input io_slave_bready,
  output io_slave_bvalid,
  output [1:0] io_slave_bresp,
  output [3:0] io_slave_bid,

  output io_slave_arready,
  input io_slave_arvalid,
  input [31:0] io_slave_araddr,
  input [3:0] io_slave_arid,
  input [7:0] io_slave_arlen,
  input [2:0] io_slave_arsize,
  input [1:0] io_slave_arburst,

  input io_slave_rready,
  output io_slave_rvalid,
  output [1:0] io_slave_rresp,
  output [63:0] io_slave_rdata,
  output io_slave_rlast,
  output [3:0] io_slave_rid,

  output [5:0] io_sram0_addr,
  output io_sram0_cen,
  output io_sram0_wen,
  output [127:0] io_sram0_wmask,
  output [127:0] io_sram0_wdata,
  input [127:0] io_sram0_rdata,
  
  output [5:0] io_sram1_addr,
  output io_sram1_cen,
  output io_sram1_wen,
  output [127:0] io_sram1_wmask,
  output [127:0] io_sram1_wdata,
  input [127:0] io_sram1_rdata,

  output [5:0] io_sram2_addr,
  output io_sram2_cen,
  output io_sram2_wen,
  output [127:0] io_sram2_wmask,
  output [127:0] io_sram2_wdata,
  input [127:0] io_sram2_rdata,

  output [5:0] io_sram3_addr,
  output io_sram3_cen,
  output io_sram3_wen,
  output [127:0] io_sram3_wmask,
  output [127:0] io_sram3_wdata,
  input [127:0] io_sram3_rdata,

  output [5:0] io_sram4_addr,
  output io_sram4_cen,
  output io_sram4_wen,
  output [127:0] io_sram4_wmask,
  output [127:0] io_sram4_wdata,
  input [127:0] io_sram4_rdata,

  output [5:0] io_sram5_addr,
  output io_sram5_cen,
  output io_sram5_wen,
  output [127:0] io_sram5_wmask,
  output [127:0] io_sram5_wdata,
  input [127:0] io_sram5_rdata,

  output [5:0] io_sram6_addr,
  output io_sram6_cen,
  output io_sram6_wen,
  output [127:0] io_sram6_wmask,
  output [127:0] io_sram6_wdata,
  input [127:0] io_sram6_rdata,

  output [5:0] io_sram7_addr,
  output io_sram7_cen,
  output io_sram7_wen,
  output [127:0] io_sram7_wmask,
  output [127:0] io_sram7_wdata,
  input [127:0] io_sram7_rdata
);
  wire clk = clock;
  wire rst = reset;

  
  wire [63:0] icache_rdata;
  wire [63:0] dcache_rdata;
  wire [3:0] dcache_rsize;
  wire icache_ren,dcache_ren;
  wire [63:0] icache_raddr,dcache_raddr;
  wire dcache_rdata_valid;
  wire icache_rdata_valid;
  wire icache_invalid;


  wire [63:0] dcache_waddr,dcache_wdata;
  wire dcache_wen;
  wire [3:0] dcache_wsize;

  wire icache_wbusy;
  wire icache_rbusy;


  wire dcache_rbusy,dcache_wbusy;
  //all store through dcache, but only mem load through dcache
  wire dcache_direct = (dcache_ren&(dcache_raddr[31:28]!=4'h8 && dcache_raddr[31:28]!=4'hf))|(dcache_wen&(dcache_waddr[31:28]!=4'h8 && dcache_waddr[31:28]!=4'hf));
  wire icache_direct = (icache_ren&(icache_raddr[31:28]!=4'h8 && icache_raddr[31:28]!=4'hf));
  wire msip_o;
  wire msip_valid_o;
  wire msip_i;
  wire tim_int_req;
  wire mtip_clear;
  toy_cpu inst_toy_cpu(
    .clk                (clk),
    .rst                (rst),
    .ex_intr            (io_interrupt),
    .icache_ren         (icache_ren),
    .icache_raddr       (icache_raddr),
    .icache_rbusy       (icache_rbusy),
    .icache_rdata       (icache_rdata[31:0]),
    .icache_rdata_valid (icache_rdata_valid),
    .icache_invalid     (icache_invalid),
    .mtip_clear         (mtip_clear),
    .msip_i             (msip_o),
    .msip_valid_i       (msip_valid_o),
    .msip_o             (msip_i),
    .tim_int_req        (tim_int_req),
    .dcache_ren         (dcache_ren),
    .dcache_raddr       (dcache_raddr),
    .dcache_rbusy       (dcache_rbusy),
    .dcache_rdata       (dcache_rdata),
    .dcache_rsize       (dcache_rsize),
    .dcache_rdata_valid (dcache_rdata_valid),
    .dcache_wbusy       (dcache_wbusy),
    .dcache_wen         (dcache_wen),
    .dcache_waddr       (dcache_waddr),
    .dcache_wdata       (dcache_wdata),
    .dcache_wsize       (dcache_wsize)
  );


  wire icache_mem_rbusy;
  wire icache_mem_ren;
  wire [3:0] icache_mem_rsize;
  wire [31:0] icache_mem_raddr;
  wire reg [63:0] icache_mem_rdata;
  wire reg icache_mem_rdata_valid;

  wire icache_mem_wbusy = 1'b0;
  wire icache_mem_wen;
  wire [3:0] icache_mem_wsize;
  wire [31:0] icache_mem_waddr;
  wire [63:0] icache_mem_wdata;

  cache inst_icache
  (
    .clk         (clk),
    .rst         (rst),
    .direct      (icache_direct),
    .invalid     (icache_invalid),
    .ren         (icache_ren),
    .raddr       (icache_raddr),
    .rsize       (4'h4),
    .rbusy       (icache_rbusy),
    .rdata       (icache_rdata),
    .rdata_valid (icache_rdata_valid),
    .wbusy       (icache_wbusy),
    .wen         (1'b0),
    .waddr       (64'b0),
    .wdata       (64'b0),
    .wsize       (4'b0),
    .io_sram0_addr  (io_sram0_addr),
    .io_sram0_cen   (io_sram0_cen),
    .io_sram0_wen   (io_sram0_wen),
    .io_sram0_wmask (io_sram0_wmask),
    .io_sram0_wdata (io_sram0_wdata),
    .io_sram0_rdata (io_sram0_rdata),
    .io_sram1_addr  (io_sram1_addr),
    .io_sram1_cen   (io_sram1_cen),
    .io_sram1_wen   (io_sram1_wen),
    .io_sram1_wmask (io_sram1_wmask),
    .io_sram1_wdata (io_sram1_wdata),
    .io_sram1_rdata (io_sram1_rdata),
    .io_sram2_addr  (io_sram2_addr),
    .io_sram2_cen   (io_sram2_cen),
    .io_sram2_wen   (io_sram2_wen),
    .io_sram2_wmask (io_sram2_wmask),
    .io_sram2_wdata (io_sram2_wdata),
    .io_sram2_rdata (io_sram2_rdata),
    .io_sram3_addr  (io_sram3_addr),
    .io_sram3_cen   (io_sram3_cen),
    .io_sram3_wen   (io_sram3_wen),
    .io_sram3_wmask (io_sram3_wmask),
    .io_sram3_wdata (io_sram3_wdata),
    .io_sram3_rdata (io_sram3_rdata),
    .mem_rbusy       (icache_mem_rbusy),
    .mem_ren         (icache_mem_ren),
    .mem_rsize       (icache_mem_rsize),
    .mem_raddr       (icache_mem_raddr),
    .mem_rdata       (icache_mem_rdata),
    .mem_rdata_valid (icache_mem_rdata_valid),
    .mem_wbusy       (icache_mem_wbusy),
    .mem_wen         (icache_mem_wen),
    .mem_wsize       (icache_mem_wsize),
    .mem_waddr       (icache_mem_waddr),
    .mem_wdata       (icache_mem_wdata)

  );

  wire dcache_mem_rbusy;
  wire dcache_mem_ren;
  wire [3:0] dcache_mem_rsize;
  wire [31:0] dcache_mem_raddr;
  wire reg [63:0] dcache_mem_rdata;
  wire reg dcache_mem_rdata_valid;

  wire dcache_mem_wbusy;
  wire dcache_mem_wen;
  wire [3:0] dcache_mem_wsize;
  wire [31:0] dcache_mem_waddr;
  wire [63:0] dcache_mem_wdata;
  cache inst_dcache
  (
    .clk         (clk),
    .rst         (rst),
    .direct      (dcache_direct),
    .invalid     (icache_invalid),
    .ren         (dcache_ren),
    .raddr       (dcache_raddr),
    .rsize       (dcache_rsize),
    .rbusy       (dcache_rbusy),
    .rdata       (dcache_rdata),
    .rdata_valid (dcache_rdata_valid),
    .wbusy       (dcache_wbusy),
    .wen         (dcache_wen),
    .waddr       (dcache_waddr),
    .wdata       (dcache_wdata),
    .wsize       (dcache_wsize),
    .io_sram0_addr  (io_sram4_addr),
    .io_sram0_cen   (io_sram4_cen),
    .io_sram0_wen   (io_sram4_wen),
    .io_sram0_wmask (io_sram4_wmask),
    .io_sram0_wdata (io_sram4_wdata),
    .io_sram0_rdata (io_sram4_rdata),
    .io_sram1_addr  (io_sram5_addr),
    .io_sram1_cen   (io_sram5_cen),
    .io_sram1_wen   (io_sram5_wen),
    .io_sram1_wmask (io_sram5_wmask),
    .io_sram1_wdata (io_sram5_wdata),
    .io_sram1_rdata (io_sram5_rdata),
    .io_sram2_addr  (io_sram6_addr),
    .io_sram2_cen   (io_sram6_cen),
    .io_sram2_wen   (io_sram6_wen),
    .io_sram2_wmask (io_sram6_wmask),
    .io_sram2_wdata (io_sram6_wdata),
    .io_sram2_rdata (io_sram6_rdata),
    .io_sram3_addr  (io_sram7_addr),
    .io_sram3_cen   (io_sram7_cen),
    .io_sram3_wen   (io_sram7_wen),
    .io_sram3_wmask (io_sram7_wmask),
    .io_sram3_wdata (io_sram7_wdata),
    .io_sram3_rdata (io_sram7_rdata),
    .mem_rbusy       (dcache_mem_rbusy),
    .mem_ren         (dcache_mem_ren),
    .mem_rsize       (dcache_mem_rsize),
    .mem_raddr       (dcache_mem_raddr),
    .mem_rdata       (dcache_mem_rdata),
    .mem_rdata_valid (dcache_mem_rdata_valid),
    .mem_wbusy       (dcache_mem_wbusy),
    .mem_wen         (dcache_mem_wen),
    .mem_wsize       (dcache_mem_wsize),
    .mem_waddr       (dcache_mem_waddr),
    .mem_wdata       (dcache_mem_wdata)
    
  );
  
  wire clint_wen;
  wire clint_ren;
  wire [31:0] clint_raddr;
  wire [31:0] clint_waddr;
  wire [63:0] clint_wdata;
  wire [3:0] clint_wsize;
  wire [63:0] clint_rdata;
  wire [3:0] clint_rsize;
  wire clint_rdata_valid;

  MemBus inst_MemBus
    (
      .clk                    (clk),
      .rst                    (rst),
      .dcache_mem_rbusy       (dcache_mem_rbusy),
      .dcache_mem_ren         (dcache_mem_ren),
      .dcache_mem_rsize       (dcache_mem_rsize),
      .dcache_mem_raddr       (dcache_mem_raddr),
      .dcache_mem_rdata       (dcache_mem_rdata),
      .dcache_mem_rdata_valid (dcache_mem_rdata_valid),
      .dcache_mem_wbusy       (dcache_mem_wbusy),
      .dcache_mem_wen         (dcache_mem_wen),
      .dcache_mem_wsize       (dcache_mem_wsize),
      .dcache_mem_waddr       (dcache_mem_waddr),
      .dcache_mem_wdata       (dcache_mem_wdata),
      .icache_mem_rbusy       (icache_mem_rbusy),
      .icache_mem_ren         (icache_mem_ren),
      .icache_mem_rsize       (icache_mem_rsize),
      .icache_mem_raddr       (icache_mem_raddr),
      .icache_mem_rdata       (icache_mem_rdata),
      .icache_mem_rdata_valid (icache_mem_rdata_valid),
      .clint_wen              (clint_wen),
      .clint_ren              (clint_ren),
      .clint_raddr            (clint_raddr),
      .clint_waddr            (clint_waddr),
      .clint_wdata            (clint_wdata),
      .clint_wsize            (clint_wsize),
      .clint_rdata            (clint_rdata),
      .clint_rsize            (clint_rsize),
      .clint_rdata_valid      (clint_rdata_valid),
      .io_master_awready      (io_master_awready),
      .io_master_awvalid      (io_master_awvalid),
      .io_master_awaddr       (io_master_awaddr),
      .io_master_awid         (io_master_awid),
      .io_master_awlen        (io_master_awlen),
      .io_master_awsize       (io_master_awsize),
      .io_master_awburst      (io_master_awburst),
      .io_master_wready       (io_master_wready),
      .io_master_wvalid       (io_master_wvalid),
      .io_master_wdata        (io_master_wdata),
      .io_master_wstrb        (io_master_wstrb),
      .io_master_wlast        (io_master_wlast),
      .io_master_bready       (io_master_bready),
      .io_master_bvalid       (io_master_bvalid),
      .io_master_bresp        (io_master_bresp),
      .io_master_bid          (io_master_bid),
      .io_master_arready      (io_master_arready),
      .io_master_arvalid      (io_master_arvalid),
      .io_master_araddr       (io_master_araddr),
      .io_master_arid         (io_master_arid),
      .io_master_arlen        (io_master_arlen),
      .io_master_arsize       (io_master_arsize),
      .io_master_arburst      (io_master_arburst),
      .io_master_rready       (io_master_rready),
      .io_master_rvalid       (io_master_rvalid),
      .io_master_rresp        (io_master_rresp),
      .io_master_rdata        (io_master_rdata),
      .io_master_rlast        (io_master_rlast),
      .io_master_rid          (io_master_rid)
    );
    

    CoreLocalInterrupt inst_CoreLocalInterrupt
    (
      .clk          (clk),
      .rst          (rst),
      .wen          (clint_wen),
      .ren          (clint_ren),
      .raddr        (clint_raddr),
      .waddr        (clint_waddr),
      .wdata        (clint_wdata),
      .wsize        (clint_wsize),
      .rsize        (clint_rsize),
      .rdata        (clint_rdata),
      .rdata_valid  (clint_rdata_valid),
      .tim_int_req  (tim_int_req),
      .mtip_clear   (mtip_clear),
      .msip_i       (msip_i),
      .msip_o       (msip_o),
      .msip_valid_o (msip_valid_o)
    );



  assign io_slave_awready = 1'b0;
  assign io_slave_wready = 1'b0;
  assign io_slave_bvalid = 1'b0;
  assign io_slave_bresp = 2'b0;
  assign io_slave_bid = 4'b0;
  assign io_slave_arready = 1'b0;
  assign io_slave_rvalid = 1'b0;
  assign io_slave_rresp = 2'b0;
  assign io_slave_rdata = 64'b0;
  assign io_slave_rlast = 1'b0;
  assign io_slave_rid = 4'b0;


endmodule
